A variable capacitance may be provided in a digital circuit by switching a number of equal unit capacitors into the circuit. In the simplest example, two unit capacitors connected in parallel provide a total capacitance equal to twice the unit capacitance. In general, N unit capacitors connected in parallel have a capacitance equal to N times the unit capacitance. Capacitances from zero up to the maximum capacitance of an array may be selected in steps as small as the unit capacitance.
Digitally selectable capacitance is useful in a variety of electronic circuits. For example, in a relaxation oscillator the frequency of the output depends on the time to charge a capacitor according to an RC time constant. Changing capacitance in the circuit changes the output frequency. Such oscillators are tunable over a wide range of output frequencies and consume low amounts of electrical power. Many other circuits, especially mixed analog—digital logic circuits, use digital capacitor arrays.
The resolution of a digital capacitor array can be defined as the minimum step in capacitance or the minimum difference between two output capacitance values. In theory, unit capacitors in a capacitor array could be made to have arbitrarily small capacitance leading to infinite precision. However, at least two effects limit the resolution that is achievable in practice. First, the unit capacitance cannot be smaller than stray or unintended capacitances. Second, it is challenging to make all unit capacitances in an array exactly equal to one another. The nominal unit capacitance must be greater than the variation in the unit capacitances of array elements.
The output capacitance of a digital capacitor array is selectable in steps corresponding to digital input values, for example, . . . n−1, n, n+1, . . . etc. If the output capacitance of a digital capacitor array always increases in response to an increase in the digital input value, then the array is said to be monotonic.
Ultimately, precision of a capacitor array and its monotonicity in response to digital input depend upon manufacturing tolerances and design. Capacitor arrays made in conjunction with other integrated circuits in a complementary metal-oxide-semiconductor (CMOS) process, for example, are subject to process variations in lithography, etch and other process modules. It is necessary to minimize the effects of these variations through innovation in unit capacitor design, array layout and digital addressing schemes.